NVMe Protocol(Queue)

NVMe has maximum 64k queue. To write data faster, the technique called Write-Combine was used. But Write-Combine breaks coherence of data. For example host queued 'A' data for address 0 and after 10ns queued 'B' data for the same address, Write-Combine results in data 'B' for address 0 if the order of queue was not changed. But PCIe MUX/DEMUX may change the order of queue so breaks data coherence. Note that PCIe uses serial data line. Write-Combine was originally used for Video Cards. (Did you see glithes sometime while video update?)

SATA never changes the order of queue. So SATA keeps data coherence.

This example(html) uses JavaScript(single-threaded) so never breaks data coherence.